Using Hierarchical Structuring Mechanisms with Petri Nets for Pld Based System Design

This paper addresses the use of hierarchical model structuring mechanisms for the design of embedded systems (in the sense of reactive real-time systems), using Reactive Petri nets. Relevant characteristics of Reactive Petri nets are briefly presented and their main roots are identified, namely Coloured Petri nets, Interpreted and Synchronised Petri nets. Two structuring techniques will be presented. The first one concerns with the integration of bus signals representation into non-autonomous Petri net models and the second one with a graphical structuring mechanism named by horizontal decomposition. This mechanism relies on the usage of macro-nodes, which have sub-nets associated with them. Three types of macro-nodes were used: macroplace, macro-transition and macro-block. The execution of the model is accomplished through the execution of the flat representation of the model. At the end, a case study is presented around a controller of a 3-cell FIFO system. High-level and low-level Petri net models were used and compared for that purpose. The implementation of the referred controller was done using programmable logic devices, namely PALs and CPLDs.